There is a tremendous variety of products, from single-chip microcomputers costing a few dollars to supercomputers costing tens of millions of dollars that can rightly claim the name "computer".

The variety of computer products is exhibited only in cost.

Computer organization refers to attributes of a system visible to the programmer.

Changes in computer technology are finally slowing down.

The textbook for this course is about the structure and function of computers.

The number of bits used to represent various data types is an example of an architectural attribute.

Interfaces between the computer and peripherals is an example of an organizational attribute.

Historically the distinction between architecture and organization has not been an important one.

A particular architecture may span many years and encompass a number of different computer models, its organization changing with changing technology.

A microcomputer architecture and organization relationship is not very close.

Changes in technology not only influence organization but also result in the introduction of more powerful and more complex architectures.

The hierarchical nature of complex systems is essential to both their design and their description.

Both the structure and functioning of a computer are, in essence, simple.

A computer must be able to process, store, move, and control data.

When data are moved over longer distances, to or from a remote device, the process is known as data transport.

Computer technology is changing at a __________ pace.

Computer _________ refers to those attributes that have a direct impact on the logical execution of a program.

Architectural attributes include __________ .

_________ attributes include hardware details transparent to the programmer.

It is a(n) _________ design issue whether a computer will have a multiply instruction.

It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system.

A __________ system is a set of interrelated subsystems.

An I/O device is referred to as a __________.

When data are moved over longer distances, to or from a remote device, the process is known as __________.

The _________ stores data.

The __________ moves data between the computer and its external environment.

A common example of system interconnection is by means of a __________.

A _________ is a mechanism that provides for communication among CPU, main memory, and I/O.

_________ provide storage internal to the CPU.

The __________ performs the computer's data processing functions.

The world's first general-purpose electronic digital computer was designed and constructed at The Ohio State University.

John Mauchly and John Eckert designed the ENIAC.

The major drawback of the EDVAC was that it had to be programmed manually by setting switches and plugging and unplugging cables.

The IAS is the prototype of all subsequent general-purpose computers.

The IAS operates by repetitively performing an instruction cycle.

Backward compatible means that the programs written for the older machines can be executed on the new machine.

A vacuum tube is a solid-state device made from silicon.

Computers are classified into generations based on the fundamental hardware technology employed.

System software was introduced in the third generation of computers.

A wafer is made of silicon and is broken up into chips which consists of many gates and/or memory cells plus a number of input and output attachment points.

IBM's System/360 was the industry's first planned family of computers.

Intel's 4004 was the first chip to contain all of the components of a CPU on a single chip.

Designers wrestle with the challenge of balancing processor performance with that of main memory and other computer components.

The Intel x86 evolved from RISC design principles and is used in embedded systems.

A common measure of performance for a processor is the rate at which instructions are executed, expressed as billions of instructions per seconds (BIPS).

The _________ was the world's first general-purpose electronic digital computer.

The Electronic Numerical Integrator and Computer project was a response to U.S. needs during _________.

The ENIAC used __________.

The ENIAC is an example of a _________ generation computer.

The __________ interprets the instructions in memory and causes them to be executed.

The memory of the IAS consists of 1000 storage locations called __________.

The __________ contains the 8-bit opcode instruction being executed.

During the _________ the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR.

Second generation computers used __________.

The __________ defines the third generation of computers.

The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate.

With the __________, Intel introduced the use of superscalar techniques that allow multiple instructions to execute in parallel.

The __________ measures the ability of a computer to complete a single task.

ARM processors are designed to meet the needs of _________.

One increment, or pulse, of the system clock is referred to as a _________.

At a top level, a computer consists of CPU, memory, and I/O components.

The basic function of a computer is to execute programs.

Program execution consists of repeating the process of instruction fetch and instruction execution.

Interrupts do not improve processing efficiency.

An I/O module cannot exchange data directly with the processor.

A key characteristic of a bus is that it is not a shared transmission medium.

Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy.

In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay.

It is not possible to connect I/O controllers directly onto the system bus.

The method of using the same lines for multiple purposes is known as time multiplexing.

Timing refers to the way in which events are coordinated on the bus.

With asynchronous timing the occurrence of events on the bus is determined by a clock.

Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance.

The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit.

A key requirement for PCIe is high capacity to support the needs of higher data rate I/O devices such as Gigabit Ethernet.

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton.

The von Neumann architecture is based on which concept?

A sequence of codes or instructions is called __________.

The processing required for a single instruction is called a(n) __________ cycle.

A(n) _________ is generated by a failure such as power failure or memory parity error.

A(n) _________ is generated by some condition that occurs as a result of an instruction execution.

The interconnection structure must support which transfer?

A bus that connects major computer components (processor, memory, I/O) is called a __________.

The __________ are used to designate the source or destination of the data on the data bus.

The data lines provide a path for moving data among system modules and are collectively called the _________.

A __________ is the high-level set of rules for exchanging packets of data between devices.

Each data path consists of a pair of wires (referred to as a __________) that transmits data one bit at a time.

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer.

The TL supports which of the following address spaces?

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects.

No single technology is optimal in satisfying the memory requirements for a computer system.

A typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system and some external.

External memory is often equated with main memory.

The processor requires its own local memory.

Cache is not a form of internal memory.

The unit of transfer must equal a word or an addressable unit.

Both sequential access and direct access involve a shared read-write mechanism.

In a volatile memory, information decays naturally or is lost when electrical power is switched off.

To achieve greatest performance the memory must be able to keep up with the processor.

Secondary memory is used to store program and data files and is usually visible to the programmer only in terms of individual bytes or words.

The L1 cache is slower than the L3 cache.

With write back updates are made only in the cache.

It has become possible to have a cache on the same chip as the processor.

All of the Pentium processors include two on-chip L1 caches, one for data and one for instructions.

Cache design for HPC is the same as that for other hardware platforms and applications.

__________ refers to whether memory is internal or external to the computer.

Internal memory capacity is typically expressed in terms of _________.

For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module.

"Memory is organized into records and access must be made in a specific linear sequence" is a description of __________.

individual blocks or records have a unique address based on physical location with __________.

For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use.

The ________ consists of the access time plus any additional time required before a second access can commence.

A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________.

A line includes a _________ that identifies which particular block is currently being stored.

__________ is the simplest mapping technique and maps each block of main memory into only one possible cache line.

When using the __________ technique all write operations made to main memory are made to the cache as well.

The key advantage of the __________ design is that it eliminates contention for the cache between the instruction fetch/decode unit and the execution unit.

The Pentium 4 _________ component executes micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers.

In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory.

A logical cache stores data using __________.

The basic element of a semiconductor memory is the memory cell.

A characteristic of ROM is that it is volatile.

RAM must be provided with a constant power supply.

The two traditional forms of RAM used in computers are DRAM and SRAM.

A static RAM will hold its data as long as power is supplied to it.

Nonvolatile means that power must be continuously supplied to the memory to preserve the bit values.

The advantage of RAM is that the data or program is permanently in main memory and need never be loaded from a secondary storage device.

Semiconductor memory comes in packaged chips.

All DRAMs require a refresh operation.

A number of chips can be grouped together to form a memory bank.

An error-correcting code enhances the reliability of the memory at the cost of added complexity.

DRAM is much costlier than SRAM.

RDRAM is limited by the fact that it can only send data to the processor once per bus clock cycle.

The prefetch buffer is a memory cache located on the RAM chip.

The SRAM on the CDRAM cannot be used as a buffer to support the serial access of a block of data.

Which properties do all semiconductor memory cells share?

One distinguishing characteristic of memory that is designated as _________ is that it is possible to both to read data from the memory and to write new data into the memory easily and rapidly.

Which of the following memory types are nonvolatile?

In a _________, binary values are stored using traditional flip-flop logic-gate configurations.

A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into it.

With _________ the microchip is organized so that a section of memory cells are erased in a single action.

__________ can be caused by harsh environmental abuse, manufacturing defects, and wear.

_________ can be caused by power supply problems or alpha particles.

The _________ exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states.

________ can send data to the processor twice per clock cycle.

__________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip.

________ increases the prefetch buffer size to 8 bits.

Theoretically, a DDR module can transfer data at a clock rate in the range of __________ MHz.

A DDR3 module transfers data at a clock rate of __________ MHz.

The ________ enables the RAM chip to preposition bits to be placed on the data bus as rapidly as possible.

Magnetic disks are the foundation of external memory on virtually all computer systems.

During a read or write operation, the head rotates while the platter beneath it stays stationary.

The width of a track is double that of the head.

There are typically hundreds of sectors per track and they may be either fixed or variable lengths.

A bit near the center of a rotating disk travels past a fixed point slower than a bit on the outside.

The disadvantage of using CAV is that individual blocks of data can only be directly addressed by track and sector.

A removable disk can be removed and replaced with another disk.

The head must generate or sense an electromagnetic field of sufficient magnitude to write and read properly.

The transfer time to or from the disk does not depend on the rotation speed of the disk.

RAID is a set of physical disk drives viewed by the operating system as a single logical drive.

RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve performance.

Because data are striped in very small strips, RAID 3 cannot achieve very high data transfer rates.

The SSDs now on the market use a type of semiconductor memory referred to as flash memory.

SSD performance has a tendency to speed up as the device is used.

Flash memory becomes unusable after a certain number of writes.

Greater ability to withstand shock and damage, improvement in the uniformity of the magnet film surface to increase disk reliability, and a significant reduction in overall surface defects to help reduce read-write errors, are all benefits of ___________.

Adjacent tracks are separated by _________.

Data are transferred to and from the disk in __________.

In most contemporary systems fixed-length sectors are used, with _________ bytes being the nearly universal sector size.

Scanning information at the same rate by rotating the disk at a fixed speed is known as the _________.

The disadvantage of _________ is that the amount of data that can be stored on the long outer tracks is only the same as what can be stored on the short inner tracks.

A __________ disk is permanently mounted in the disk drive, such as the hard disk in a personal computer.

When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________.

The set of all the tracks in the same relative position on the platter is referred to as a _________.

The sum of the seek time and the rotational delay equals the _________, which is the time it takes to get into position to read or write.

__________ is the standardized scheme for multiple-disk database design.

RAID level ________ has the highest disk overhead of all RAID types.

A _________ is a high-definition video disk that can store 25 Gbytes on a single layer on a single side.

________ is when the disk rotates more slowly for accesses near the outer edge than for those near the center.

The areas between pits are called _________.

A set of I/O modules is a key element of a computer system.

An I/O module must recognize one unique address for each peripheral it controls.

I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes.

It is the responsibility of the processor to periodically check the status of the I/O module until it finds that the operation is complete.

With isolated I/O there is a single address space for memory locations and I/O devices.

A disadvantage of memory-mapped I/O is that valuable memory address space is used up.

The disadvantage of the software poll is that it is time consuming.

With a daisy chain the processor just picks the interrupt line with the highest priority.

Bus arbitration makes use of vectored interrupts.

The rotating interrupt mode allows the processor to inhibit interrupts from certain devices.

Because the 82C55A is programmable via the control register, it can be used to control a variety of simple peripheral devices.

When large volumes of data are to be moved, a more efficient technique is direct memory access (DMA).

An I/O channel has the ability to execute I/O instructions, which gives it complete control over I/O operations.

A multipoint external interface provides a dedicated line between the I/O module and the external device.

A Thunderbolt compatible peripheral interface is no more complex than that of a simple USB device.

The _________ contains logic for performing a communication function between the peripheral and the bus.

The most common means of computer/user interaction is a __________.

The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices.

An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an _________.

An I/O module that is quite primitive and requires detailed control is usually referred to as an _________.

The _________ command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral.

The ________ command is used to activate a peripheral and tell it what to do.

________ is when the DMA module must force the processor to suspend operation temporarily.

The 8237 DMA is known as a _________ DMA controller.

________ is a digital display interface standard now widely adopted for computer monitors, laptop displays, and other graphics and video interfaces.

The ________ layer is the key to the operation of Thunderbolt and what makes it attractive as a high-speed peripheral I/O technology.

The Thunderbolt protocol _________ layer is responsible for link maintenance including hot-plug detection and data encoding to provide highly efficient data transfer.

The ________ contains I/O protocols that are mapped on to the transport layer.

A ________ is used to connect storage systems, routers, and other peripheral devices to an InfiniBand switch.

A ________ connects InfiniBand subnets, or connects an InfiniBand switch to a network such as a local area network, wide area network, or storage area network.

Scheduling and memory management are the two OS functions that are most relevant to the study of computer organization and architecture.

The end user is concerned mainly with the computer's architecture.

The most important system program is the OS.

The ABI is the boundary between hardware and software.

The OS must determine how much processor time is to be devoted to the execution of a particular user program.

With a batch operating system the user does not have direct access to the processor.

Privileged instructions are certain instructions that are designated special and can be executed only by the monitor.

Uniprogramming is the central theme of modern operating systems.

Both batch multiprogramming and time sharing use multiprogramming.

An interrupt is a hardware-generated signal to the processor.

Swapping is an I/O operation.

With demand paging it is necessary to load an entire process into main memory.

The Pentium II includes hardware for both segmentation and paging.

ARM provides a versatile virtual memory system architecture that can be tailored to the needs of the embedded system designer.

Managers are users of domains that must observe the access permissions of the individual sections and/or pages that make up that domain.

The __________ is a program that controls the execution of application programs and acts as an interface between applications and the computer hardware.

Facilities and services provided by the OS that assist the programmer in creating programs are in the form of _________ programs that are not actually part of the OS but are accessible through the OS.

The _________ defines the repertoire of machine language instructions that a computer can follow.

The _________ defines the system call interface to the operating system and the hardware resources and services available in a system through the user instruction set architecture.

The ________ gives a program access to the hardware resources and services available in a system through the user instruction set architecture supplemented with high-level language library calls.

A _________ system works only one program at a time.

A _________ is a special type of programming language used to provide instructions to the monitor.

The _________ scheduler determines which programs are admitted to the system for processing.

The ________ scheduler is also known as the dispatcher.

A _________ is an actual location in main memory.

________ is when the processor spends most of its time swapping pages rather than executing instructions.

Virtual memory schemes make use of a special cache called a ________ for page table entries.

With _________ the virtual address is the same as the physical address.

A _________ is a collection of memory regions.

The OS maintains a __________ for each process that shows the frame location for each page of the process.

Our primary counting system is based on binary digits to represent numbers.

The decimal system has a radix of 100.

Negative powers of 10 are used to represent the positions of the numbers for decimal fractions.

A number with both an integer and fractional part has digits raised to both positive and negative powers of 10.

In any number, the rightmost digit is referred to as the most significant digit.

A number cannot be converted from binary notation to decimal notation.

There are 50 tens in the number 509.

The decimal system is a special case of a positional number system with radix 10 and with digits in the range 0 through 9.

Although convenient for computers, the binary system is exceedingly cumbersome for human beings.

A nibble is a grouping of four decimal digits.

Hexadecimal notation is only used for representing integers.

It is extremely easy to convert between binary and hexadecimal notation.

Hexadecimal notation is more compact than binary notation.

A sequence of hexadecimal digits can be thought of as representing an integer in base 10.

Because of the inherent binary nature of digital computer components, all forms of data within computers are represented by various binary codes.

The decimal system has a base of _________.

Which digit represents "hundreds" in the number 8732?

Which of the following is correct?

In the number 3109, the 3 is referred to as the _________.

In the number 3109, the 9 is referred to as the _________.

Numbers in the binary system are represented to the _________.

Hexadecimal has a base of _________.

The binary string 110111100001 is equivalent to __________.

The _________ system uses only the numbers 0 and 1.

Decimal "10" is __________ in binary.

Decimal "10" is _________ in hexadecimal.

Four bits is called a _________.

Another term for "base" is __________.

In the number 472.156 the 2 is the _________.

Binary 0101 is hexadecimal _________.

One drawback of sign-magnitude representation is that there are two representations of 0.

Both sign-magnitude representation and twos complement representation use the most significant bit as a sign bit.

It is not necessary for the ALU to signal when overflow occurs.

Overflow can only occur if there is a carry.

Compared with addition and subtraction, multiplication is a complex operation, whether performed in hardware of software.

For each 1 on the multiplier, an add and a shift operation are required; but for each 0 only a shift is required.

Addition and subtraction can be performed on numbers in twos complement notation by treating them as unsigned integers.

Booth's algorithm performs more additions and subtractions than a straightforward algorithm.

With a fixed-point notation it is possible to represent a range of positive and negative integers centered on or near 0.

An advantage of biased representation is that nonnegative floating-point numbers can be treated as integers for comparison purposes.

For base 2 representation, a normal number is one in which the most significant bit of the significand is zero.

Actual floating-point representations include a special bit pattern to designate zero.

The numbers represented in floating-point notation are not spaced evenly along the number line, as are fixed-point numbers.

Overflow is a less serious problem because the result can generally be satisfactorily approximated by 0.

One of the trade-offs of floating-point math is that many calculations produce results that are not exact and have to be rounded to the nearest value that the notation can represent.

The most common scheme in implementing the integer portion of the ALU is:

__________ representation is almost universally used as the processor representation for integers.

Moving the sign bit to the new leftmost position and filling in with copies of the sign bit is called _________.

In ________ representation the rule for forming the negation of an integer is to invert the sign bit.

________ is when the result may be larger than can be held in the word size being used.

__________ involves the generation of partial products, one for each digit in the multiplier, which are then summed to produce the final product.

Although considered obsolete, the term _________ is sometimes used instead of significand.

Negative numbers less than -(2 - 2^-23) x 2 128 are called _________.

Negative numbers greater than 2^-127 are called _________.

Positive numbers less than 2^-127 are called ________.

Positive numbers greater than (2 - 2^-23) x 2^-128 are called _________.

_________ formats extend a supported basic format by providing additional bits in the exponent and in the significand.

_________ are included in IEEE 754 to handle cases of exponent underflow.

__________ is when a positive exponent exceeds the maximum possible exponent value.

__________ means that the number is too small to be represented and it may be reported as 0.

The operation of the digital computer is based on the storage and processing of binary data.

Claude Shannon, a research assistant in the Electrical Engineering Department at M.I.T., proposed the basic principles of Boolean algebra.

In the absence of parentheses, the AND operation takes precedence over the OR operation.

Logical functions are implemented by the interconnection of decoders.

The delay by the propagation time of signals through the gate is known as the gate delay.

A combinational circuit consists of n binary inputs and m binary outputs.

Any Boolean function can be implemented in electronic form as a network of gates.

A Boolean function can be realized in the sum of products (SOP) form but not in the product of sums (POS) form.

"Don't care" conditions are when certain combinations of values of variables never occur, and therefore the corresponding output never occurs.

The value to be loaded into the program counter can come from a binary counter, the instruction register, or the output of the ALU.

In general, a decoder has n inputs and 2^n outputs.

Combinational circuits are often referred to as "memoryless" circuits because their output depends only on their current input and no history of prior inputs is retained.

Binary addition is exactly the same as Boolean algebra.

Events in the digital computer are synchronized to a clock pulse so that changes occur only when a clock pulse occurs.

A register is a digital circuit used within the CPU to store one or more bits of data.

The operand ________ yields true if and only if both of its operands are true.

The operation _________ yields true if either or both of its operands are true.

The unary operation _________ inverts the value of its operand.

A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals.

Which of the following is a functionally complete set?

For more than four variables an alternative approach is a tabular technique referred to as the _________ method.

________ are used in digital circuits to control signal and data routing.

________ is implemented with combinational circuits.

The ________ exists in one of two states and, in the absence of input, remains in that state.

The ________ flip-flop has two inputs and all possible combinations of input values are valid.

A _________ accepts and/or transfers information serially.

Counters can be designated as _________.

CPUs make use of _________ counters, in which all of the flip-flops of the counter change at the same time.

The _________ table provides the value of the next output when the inputs and the present output are known, which is exactly the information needed to design the counter or any sequential circuit.

A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs.

One boundary where the computer designer and the computer programmer can view the same machine is the machine instruction set.

The operation to be performed is specified by a binary code known as the operation code.

The address of the next instruction to be fetched must be a real address, not a virtual address.

It has become common practice to use a symbolic representation of machine instructions.

A high-level language expresses operations in a basic form involving the movement of data to or from registers.

One of the traditional ways of describing processor architecture is in terms of the number of addresses contained in each instruction.

Memory references are faster than register references.

The instruction set is the programmer's means of controlling the processor.

Addresses are a form of data.

Not all machine languages include numeric data types.

ARM processors support data types of 8 (byte), 16 (halfword), and 32 (word) bits in length.

Most machines provide the basic arithmetic operations of add, subtract, multiply, and divide.

A branch can be either forward or backward.

Procedures do not allow programming tasks to be subdivided into smaller units.

The focus of MMX technology is multimedia programming.

The ________ specifies the operation to be performed.

A(n) _________ expresses operations in a concise algebraic form using variables.

There must be ________ instructions for moving data between memory and the registers.

________ instructions operate on the bits of a word as bits rather than as numbers, providing capabilities for processing any other type of data the user may wish to employ.

_________ instructions provide computational capabilities for processing number data.

_______ instructions are needed to transfer programs and data into memory and the results of computations back out to the user.

The x86 data type that is a signed binary value contained in a byte, word, or doubleword, using twos complement representation is _________.

The most fundamental type of machine instruction is the _________ instruction.

The _________ instruction includes an implied address.

Which of the following is a true statement?

The entire set of parameters, including return address, which is stored for a procedure invocation is referred to as a _________.

Which ARM operation category includes logical instructions (AND, OR, XOR), add and subtract instructions, and test and compare instructions?

In the ARM architecture only _________ instructions access memory locations.

Which data type is defined in MMX?

A branch instruction in which the branch is always taken is _________.

The value of the mode field determines which addressing mode is to be used.

In a system without virtual memory, the effective address is a virtual address or a register.

The disadvantage of immediate addressing is that the size of the number is restricted to the size of the address field.

With direct addressing, the length of the address field is usually less than the word length, thus limiting the address range.

Register addressing is similar to direct addressing with the only difference being that the address field refers to a register rather than a main memory address.

Register indirect addressing uses the same number of memory references as indirect addressing.

Three of the most common uses of stack addressing are relative addressing, base-register addressing, and indexing.

The method of calculating the EA is the same for both base-register addressing and indexing.

Typically an instruction set will include both preindexing and postindexing.

The x86 is equipped with a variety of addressing modes intended to allow the efficient execution of high-level languages.

The base with index and displacement mode sums the contents of the base register, the index register, and a displacement to form the effective address.

The memory transfer rate has not kept up with increases in processor speed.

For addresses that reference memory the range of addresses that can be referenced is not related to the number of address bits.

The principal price to pay for variable-length instructions is an increase in the complexity of the processor.

One advantage of linking the addressing mode to the operand rather than the opcode is that any addressing mode can be used with any opcode.

The advantage of __________ is that no memory reference other than the instruction fetch is required to obtain the operand.

The principal advantage of ___________ addressing is that it is a very simple form of addressing.

__________ has the advantage of large address space, however it has the disadvantage of multiple memory references.

The advantages of _________ addressing are that only a small address field is needed in the instruction and no time-consuming memory references are required.

__________ has the advantage of flexibility, but the disadvantage of complexity.

For _________, the address field references a main memory address and the referenced register contains a positive displacement from that address.

Indexing performed after the indirection is __________.

For the _________ mode, the operand is included in the instruction.

The only form of addressing for branch instructions is _________ addressing.

Which of the following interrelated factors go into determining the use of the addressing bits?

_________ is a principle by which two variables are independent of each other.

The _________ was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer.

The __________ byte consists of three fields: the Scale field, the Index field and the Base field.

All instructions in the ARM architecture are __________ bits long and follow a regular format.

__________ is a design principle employed in designing the PDP-10 instruction set.

The processor needs to store instructions and data temporarily while an instruction is being executed.

The control unit (CU) does the actual computation or processing of data.

Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy.

Condition codes facilitate multiway branches.

The allocation of control information between registers and memory are not considered to be a key design issue.

Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity.

The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline.

A control hazard occurs when two or more instructions that are already in the pipeline need the same resource.

One of the major problems in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline.

The predict-never-taken approach is the most popular of all the branch prediction methods.

It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired.

Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed.

An interrupt is generated from software and it is provoked by the execution of an instruction.

While the processor is in user mode the program being executed is unable to access protected system resources or to change mode, other than by causing an exception to occur.

The exception modes have full access to system resources and can change modes freely.

__________ are a set of storage locations.

The ________ controls the movement of data and instructions into and out of the processor.

________ registers may be used only to hold data and cannot be employed in the calculation of an operand address.

__________ are bits set by the processor hardware as the result of operations.

The _________ contains the address of an instruction to be fetched.

The _________ contains a word of data to be written to memory or the word most recently read.

The ________ determines the opcode and the operand specifiers.

_________ is a pipeline hazard.

A ________ hazard occurs when there is a conflict in the access of an operand location.

A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence.

The _________ is a small cache memory associated with the instruction fetch stage of the pipeline.

The _________ stage includes ALU operations, cache access, and register update.

________ is used for debugging.

The ARM architecture supports _______ execution modes.

The OS usually runs in ________.

Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept.

Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction program.

The major cost in the life cycle of a system is hardware.

It is common for programs, both system and application, to continue to exhibit new bugs after years of operation.

Procedure calls and returns are not important aspects of HLL programs.

The register file is on the same chip as the ALU and control unit.

The register file employs much shorter addresses than addresses for cache and memory.

To handle any possible pattern of calls and returns the number of register windows would have to be unbounded.

Cache memory is a much faster memory than the register file.

The cache is capable of handling global as well as local variables.

With simple, one cycle instructions, there is little or no need for microcode.

When using graph coloring, nodes that share the same color cannot be assigned to the same register.

Almost all RISC instructions use simple register addressing.

RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations.

Unrolling can improve performance by increasing instruction parallelism by improving pipeline performance.

_________ determines the control and pipeline organization.

The Patterson study examined the dynamic behavior of _________ programs, independent of the underlying architecture.

_________ is the fastest available storage device.

The first commercial RISC product was _________.

_________ instructions are used to position quantities in registers temporarily for computational operations.

Which stage is required for load and store operations?

A ________ instruction can be used to account for data and branch delays.

The instruction location immediately following the delayed branch is referred to as the ________.

A tactic similar to the delayed branch is the _________, which can be used on LOAD instructions.

The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses, registers, and the ALU.

All MIPS R series processor instructions are encoded in a single ________ word format.

A _________ architecture is one that makes use of more, and more fine-grained pipeline stages.

The R4000 can have as many as _______ instructions in the pipeline at the same time.

SPARC refers to an architecture defined by ________.

The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.

The superscalar approach has now become the standard method for implementing high-performance microprocessors.

In a traditional scalar organization there is a single pipelined functional unit for integer operations and one for floating-point operations.

In the scalar organization there are multiple functional units, each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure.

The superscalar approach depends on the ability to execute multiple instructions in parallel.

True data dependency is also called flow dependency or read after write (RAW) dependency.

Resources include: memories, caches, buses, and register-file ports.

Machine parallelism exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping.

The simplest instruction issue policy is to issue instructions in the exact order that would be achieved by sequential execution (in-order issue) and to write results in that same order (in-order completion).

In-order completion requires more complex instruction issue logic than out-of-order completion.

The reorder buffer is temporary storage for results completed out of order that are then committed to the register file in program order.

Register renaming eliminates antidependencies and output dependencies.

In effect, the Pentium 4 architecture implements a CISC instruction set architecture on a RISC microarchitecture.

The schedulers are responsible for retrieving micro-ops from the micro-op queues and dispatching these for execution.

ARM architecture has yet to implement superscalar techniques in the instruction pipeline.

The Cortex-A8 targets a wide variety of mobile and consumer applications including mobile phones, set-top boxes, gaming consoles and automotives navigation/entertainment systems.

The superscalar approach can be used on __________ architecture.

The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines.

Which of the following is a fundamental limitation to parallelism with which the system must cope?

The situation where the second instruction needs data produced by the first instruction to execute is referred to as __________.

The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed.

________ refers to the process of initiating instruction execution in the processor's functional units.

Instead of the first instruction producing a value that the second instruction uses, with ___________ the second instruction destroys a value that the first instruction uses.

________ indicates whether this micro-op is scheduled for execution, has been dispatched for execution, or has completed execution and is ready for retirement.

__________ exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping.

_________ is determined by the number of instructions that can be fetched and executed at the same time and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions.

________ is a protocol used to issue instructions.

________ is used in scalar RISC processors to improve the performance of instructions that require multiple cycles.

Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance?

The ________ introduced a full-blown superscalar design with out-of-order execution.

Utilizing a branch target buffer (BTB), the _________ uses a dynamic branch prediction strategy based on the history of recent executions of branch instructions.

Symmetric multiprocessors (SMPs) are one of the earliest, and still the most common, example of parallel organization.

The key to the design of a supercomputer or array processor is to recognize that the main task is to perform arithmetic operations on arrays or vectors of floating-point numbers.

The term SMP refers to a computer hardware architecture and also to the operating system behavior that reflects that architecture.

With multithreading the instruction stream is divided into several smaller streams, known as threads, such that the threads can be executed in parallel.

An attractive feature of an SMP is that the existence of multiple processors is transparent to the user.

The main drawback of the bus organization is reliability.

An L1 cache that does not connect directly to the bus cannot engage in a snoopy protocol.

With a write-update protocol there can be multiple readers but only one writer at a time.

The function of switching applications and data resources over from a failed system to an alternative system in the cluster is referred to as failback.

The most important measure of performance for a processor is the rate at which it executes instructions.

An SMP operating system manages processor and other computer resources so that the user perceives a single operating system controlling system resources.

The objective with NUMA is to maintain a transparent system wide memory while permitting multiple multiprocessor nodes, each with its own bus or other internal interconnect system.

Software cache coherence schemes attempt to avoid the need for additional hardware circuitry and logic by relying on the compiler and operating system to deal with the problem.

Both clusters and symmetric multiprocessors provide a configuration with multiple processors to support high-demand applications.

Snoopy protocols are not suitable for a bus-based multiprocessor.

_________ causes results issuing from one functional unit to be fed immediately into another functional unit and so on.

With ________ instructions are simultaneously issued from multiple threads to the execution units of a superscalar processor.

The ________ contains control fields, such as the vector count, that determine how many elements in the vector registers are to be processed.

Replicating the entire processor on a single chip with each processor handling separate threads is _________.

A ________ is a dispatchable unit of work within a process that includes a processor context and its own data area for a stack.

An operation that switches the processor from one process to another by saving all the process control data, register, and other information for the first and replacing them with the process information for the second is:

Hardware-based solutions are generally referred to as cache coherence _______.

A __________ is an instance of a program running on a computer.

SMPs, clusters, and NUMA systems fit into the ________ category of computer systems.

A _________ problem arises when multiple copies of the same data can exist in different caches simultaneously, and if processors are allowed to update their own copies freely, an inconsistent view of memory can result.

With no multithreading, _________ is the simple pipeline found in traditional RISC and CISC machines.

Uniprocessors fall into the _______ category of computer systems.

Vector and array processors fall into the ________ category of computer systems.

Which of the following is an approach to vector computation?

A taxonomy first introduced by _______ is still the most common way of categorizing systems with parallel processing capability.

The organizational changes in processor design have primarily been focused on increasing instruction-level parallelism so that more work could be done in each clock cycle.

With superscalar organization increased performance can be achieved by increasing the number of parallel pipelines.

The increasingly difficult engineering challenge related to processor logic is one of the reasons that an increasing fraction of the processor chip is devote to the simpler memory logic.

The demand on power requirements has not grown as chip density and clock frequency have risen.

As chip transistor density has increased, the percentage of chip area devoted to memory has decreased.

The potential performance benefits of a multicore organization depend on the ability to effectively exploit the parallel resources available to the application.

Database management systems and database applications are one area in which multicore systems can be used effectively.

Even if an individual application does not scale to take advantage of a large number of threads, it is still possible to gain from multicore architecture by running multiple instances of the application in parallel.

With hybrid threading each major module is single threaded and the principal coordination involves synchronizing all the threads with a timeline thread.

The ARM11 MPCore is an example of the L1 cache being divided into instruction and data caches.

An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is not replicated at the shared cache level.

A potential advantage to having only dedicate L2 caches on the chip is that each core enjoys more rapid access to its private L2 cache.

The thermal management unit monitors digital sensors for high-accuracy die temperature measurements.

The Advanced Programmable Interrupt controller (APIC) monitors thermal conditions and CPU activity and adjusts voltage levels and power consumption appropriately.

A multicore computer combines two or more processors on a single piece of silicon.

With _______, register banks are replicated so that multiple threads can share the use of pipeline resources.

_________ is where individual instructions are executed through a pipeline of stages so that while one instruction is executing in one stage of the pipeline, another instruction is executing in another stage of the pipeline.

_________ is when multiple pipelines are constructed by replicating execution resources, enabling parallel execution of instructions in parallel pipelines so long as hazards are avoided.

One way to control power density is to use more of the chip area for ________.

Lotus Domino or Siebel CRM are examples of ___________ applications.

Oracle database, SAP, and PeopleSoft are examples of ________ applications.

_______ applications that can benefit directly from multicore resources include application servers such as Sun's Java Application Server, BEA's Weblogic, IBM's Websphere, and the open-source Tomcat application server.

Putting rendering on one processor, AI on another, and physics on another is an example of _________ threading.

A loop that iterates over an array of data can be split up into a number of smaller parallel loops in individual threads that can be scheduled in parallel when using ________ threading.

The _________ is an example of splitting off a separate, shared L3 cache, with dedicated L1 and L2 caches for each core processor.

The ________ connects to the external bus, known as the Front Side Bus, which connects to main memory, I/O controllers, and other processor chips.

The Intel Core i7-990X, introduced in 2008, implements ______ x86 SMT processors, each with a dedicated L2 cache, and with a shared L3 cache.

Processors are called ________.

The ________ feature enables moving dirty data from one CPU to another without writing to L2 and reading the data back in from external memory.

The ________ is responsible for maintaining coherency among L1 data caches.