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In this video we take a look at the 0:02 fetch to code 0:03 execute cycle including its effect on 0:06 the various registers we've previously 0:12 [Music] 0:14 discussed a computer is defined Definition 0:17 as an electronic device that takes an 0:20 input 0:22 processes data 0:25 and delivers output 0:29 in this simple example you can see we're 0:31 taking the input 5 0:35 we're multiplying it by 2 that's our 0:37 process 0:39 and we're outputting 10. 0:44 but this could be way more complex for 0:46 example of a game console 0:48 the input could be the buttons you press 0:50 on a controller 0:53 the processes would then be carried out 0:55 by the console itself 0:59 and the output would be some form of 1:01 update to a monitor 1:02 and sound out for a speaker possibly 1:04 vibration feedback through the 1:06 controller 1:10 to process data a computer follows a set 1:13 of instructions 1:14 known as a computer program 1:18 if we take the lid off a typical desktop 1:20 computer we can identify 1:22 two critical components the memory 1:26 that stores the program and the central 1:29 processing unit or processor 1:31 which is under this large fan and 1:33 carries out the instructions 1:37 a computer carries out its function by 1:40 fetching 1:41 instructions decoding them and then 1:43 executing them 1:44 in a continuous repetitive cycle 1:46 billions of times a second 1:48 let's look at each of these stages in a 1:50 little more detail Fetch 1:53 so let's start with the fetch stage the 1:55 very first thing that happens 1:57 is the program counter is checked as it 2:00 holds the address 2:01 of the next instruction to be executed 2:07 the address stored is then copied into 2:09 the memory address register 2:14 the address is then sent along the 2:16 address bus to main memory 2:18 where it waits to receive a signal from 2:21 the control 2:22 bus so it knows what to do 2:27 as we want to read the data that's 2:29 stored in memory address 2:30 0 0 0 0 the control unit sends 2:34 a read signal along the control bus to 2:36 main memory 2:41 now main memory knows the data needs to 2:44 be read 2:45 the content stored in memory address 000 2:49 can be sent along the data bus to the 2:51 memory data register 2:56 now as we're currently in the process of 2:58 fetching an instruction 3:00 the data received by the memory data 3:03 register gets copied 3:04 into the current instruction register 3:11 the instruction effectively has now been 3:14 fetched from memory 3:16 just before we proceed to the decode 3:18 phase we now 3:19 increment the program counter so that 3:22 the address it contains 3:24 points to the address of the next 3:26 instruction which will need to be 3:30 executed 3:32 the instruction now being held in the 3:33 current instruction register 3:35 is ready to be decoded 3:39 now as we mentioned in the previous 3:41 video the instruction is made up of two 3:43 parts 3:44 we have the op code that's what it is we 3:47 need to do 3:50 and we have the operand what are we 3:53 going to do it to 3:55 now the operand could contain the actual 3:57 data 3:58 or indeed it could contain an address of 4:01 where the data is to be found 4:06 by decoding this instruction we can see 4:08 the operation we need 4:10 is a load operation so we need to load 4:14 the contents of memory location0101 4:18 into the cpus accumulator 4:25 in the exam a simple model will be used 4:27 to describe the 4:29 structure of any given instruction 4:32 you're not going to be expected to 4:34 define how an opcode is made up 4:36 but simply to interpret opcodes in the 4:39 given context of an exam 4:40 question in the example here 4:44 you can see there's a total of 16 4:46 different opcodes available 4:48 and this is because we're using four 4:50 bits for our representation 4:56 so now we've fetched the instruction and 4:59 we've decoded it so we know what we need 5:00 to do 5:01 we're finally ready to execute it 5:05 so we now send address 0101 5:08 to the memory dress register 5:13 now we're in the memory address register 5:15 we can finally send the address 5:18 down the address bus to main memory 5:24 this time we want to read the data 5:26 that's stored in memory 5:28 and so the control unit again sends a 5:30 read signal along the control bus 5:36 so main memories now receive an address 5:38 and a read signal 5:40 so the content stored at memory location 5:43 0101 5:44 can now be sent along the data bus back 5:46 to the cpu 5:47 and into the memory data register 5:54 finally the contents of the memory data 5:56 register are copied to the accumulator 5:59 and this is one of a number of general 6:00 purpose registers found in the cpu 6:04 this first instruction is now complete Branching 6:11 so what does this program actually do 6:14 you should be able to work it through 6:16 carefully and figure it out 6:19 we're now pointing instructions zero 6:21 zero zero one in the program counter 6:23 and we're ready to fetch the second 6:25 instruction 6:27 at the end of this video we're gonna 6:29 provide you with the answer 6:34 so let's talk a second about programs 6:37 that branch 6:40 on the left here we have a very simple 6:42 piece of pseudo code 6:44 line zero says first execute this line 6:46 of code 6:47 line 1 now execute this line and then 6:50 line 2 says 6:52 if the age is greater than 18 then 6:56 we're going to execute lines 3 and 4 6:58 otherwise 6:59 we're going to execute lines six and 7:02 seven 7:03 so this program doesn't necessarily 7:05 follow strictly in sequence from line 7:07 zero through to seven there's a chance 7:10 here the program may branch and jump 7:14 around 7:16 so we're going to pretend that this 7:17 program has been loaded into memory 7:20 each line of code on the left here has 7:23 ended up 7:24 as a location in memory now this is not 7:27 strictly how this would happen in this 7:28 one-to-one way 7:29 but for the purpose of example it's 7:31 absolutely fine 7:35 so the program counter starts by 7:37 pointing to memory address zero 7:39 and we fetch the first instruction 7:41 decode it and execute it 7:44 it then updates and tells us the next 7:47 instruction 7:48 is zero zero zero one because remember 7:50 the program counter is being incremented 7:52 so we fetch it decode it and we execute 7:55 line one of our program 7:59 we then fetch line two which in binary 8:01 is one 8:02 zero 8:06 now at this point depending on what 8:10 happens during the execution 8:11 of line two the program may be required 8:15 to fetch line three from memory or 8:18 line five from memory 8:25 so let's look at how this actually works 8:27 because we've said the program counter 8:28 simply gets incremented 8:31 well in the current instruction register 8:33 we have an instruction with the op code 8:36 0 1 1 0. 8:41 now when we look this up in the decode 8:43 unit we discover that this 8:45 code means branch always 8:51 this replaces the value held in the 8:54 program counter 8:56 with the contents of the operand that's 8:58 the second part of the instruction 9:01 from the current instruction register so 9:03 this case 9:04 one zero zero one 9:09 now when the next fetch cycle begins the 9:12 program counter is obviously checked 9:14 and as its contents have been previously 9:16 updated to a new memory location 9:19 and not simply incremented the program 9:22 effectively is able to jump 9:24 around memory 9:28 so having watched this video you should 9:30 be able to answer the following key 9:32 question 9:33 how does a cpu work 9:39 okay so let's um answer the question we 9:41 posed 9:42 earlier what did that program actually 9:48 do 9:50 so this is the first fetch to code 9:53 execute cycle 9:55 and this is the one that we ran through 9:57 in detail earlier 9:58 it effectively loaded the contents of 10:01 the memory 10:02 stored at location location0101 10:05 into the accumulator in other words 10:08 the dna number 3 is moved 10:11 from memory into the cpu 10:18 we then proceed onto the second fetch 10:20 decode execute cycle 10:23 now this one adds the contents of memory 10:27 located at 0 1 1 0 10:30 to the current contents of the 10:32 accumulator 10:34 so in other words the dna number one 10:38 because that's what's stored at address 10:40 zero one one zero 10:43 is added to the number three that was in 10:45 the accumulator 10:46 the results are stored back over the 10:48 accumulator 10:49 so effectively we've done three plus one 10:53 equals four 10:58 the third fetch to code execute cycle 11:00 stores the contents which are in the 11:02 accumulator 11:03 into memory location zero one one one 11:07 and that's because the op code the first 11:09 part of this current instruction 11:10 zero zero one one is the command to 11:13 store when we look it up in the decoder 11:15 unit 11:16 so in other words the result of the 11:17 previous calculation three plus one 11:19 equals four 11:20 is now written back into main memory 11:28 the fourth fetch decode execute cycle 11:30 outputs the contents of the accumulator 11:33 remember they were copied into main 11:34 memory but they're still held in the 11:35 accumulator 11:37 so in this simple abstraction the number 11:40 four is now 11:41 output to the user so they can see the 11:43 result of the calculation 11:49 the fifth and final fetch code execute 11:51 cycle 11:52 brings a halt to the current program 11:58 so this very simple program which has 12:01 five 12:02 fetch decode execute cycles has 12:04 performed the calculation 12:06 three plus one is then stored the result 12:09 in main memory 12:10 and displayed the result four to the 12:12 user 12:13 and in a high-level language this may 12:15 look something very similar to the 12:17 following two lines of code 12:20 sum variable equals num1 plus num2 12:24 print sum to the user 12:27 so you can start to get an appreciation 12:29 here of how the high level code you 12:32 write actually ends up being fetched 12:34 decoded 12:35 and executed inside a processor 12:38 of course your processor is doing 12:40 billions and billions of these 12:42 operations a second 12:43 which when you think about it is really 12:45 very impressive 12:52 [Music] 13:03 you. make 10 questions for a standerd of a level

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