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ISA RISC-V
Quiz by Gabriele Dessimone
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10 questions
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- Q1What does ISA stand for in the context of RISC-V?International Standards AssociationInstruction Set ArchitectureIntegrated System ArchitectureIntelligent System Automation30s
- Q2What is the width of the RISC-V register file?16-bit or 32-bit32-bit or 128-bit64-bit or 128-bit32-bit or 64-bit30s
- Q3What is the maximum length of an instruction in RISC-V?128 bits64 bits32 bits16 bits30s
- Q4What is the purpose of the RISC-V 'compress' extension?To increase the speed of code executionTo add support for floating-point operationsTo add support for virtual memoryTo reduce the size of code by compressing pairs of 16-bit instructions into one 32-bit instruction30s
- Q5Which RISC-V privilege mode provides the most access and control?Supervisor modeHypervisor modeUser modeMachine mode30s
- Q6What is the purpose of the RISC-V 'Zicsr' extension?To provide access to control and status registersTo add support for floating-point operationsTo increase the number of general purpose registersTo provide virtual memory support30s
- Q7What is the purpose of the RISC-V 'RV32I' instruction set?To provide support for the 64-bit RISC-V architectureTo add support for SIMD instructionsTo provide support for the 32-bit RISC-V architectureTo add support for virtualization30s
- Q8What is the RISC-V 'Fence' instruction used for?To synchronize memory access between threads or processesTo multiply two integers togetherTo load data from memory into a registerTo perform a function call to a specific address30s
- Q9In RISC-V, what is the purpose of the 'CSR' register?To store the return address of a functionTo allow for conditional branching based on a comparisonTo store the result of a mathematical operationTo provide a mechanism for accessing control and status registers30s
- Q10What is the RISC-V 'M' extension used for?To add support for SIMD instructionsTo add support for integer multiplication and divisionTo add support for virtual memoryTo add support for floating-point operations30s